`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date:    14:59:33 02/13/2009 
// Design Name: 
// Module Name:    alupipe 
// Project Name: 
// Target Devices: 
// Tool versions: 
// Description: 
//
// Dependencies: 
//
// Revision: 
// Revision 0.01 - File Created
// Additional Comments: 
//
//////////////////////////////////////////////////////////////////////////////////

module regN (D, Q, clk);
	
parameter N=32;

	
input [N-1:0] D;
	
output [N-1:0] Q;
	
input clk;
	
	

reg [N-1:0] Q;
	

always @(posedge clk) 
begin
	
Q=D;
	

end



endmodule




module alupipe( dbus, abus, bbus,Cin, S, shamt, clk,imm2,signext,pipedabus,Cout);
	

output [31:0] dbus,pipedbbus,pipedabus;
	
input [31:0] abus, bbus,signext;
	
input Cin, clk,imm2;
	
input [3:0] S;
input [4:0] shamt;
output Cout;
	
	

wire [31:0] abus,bbus,d,wirepipedbbus,pipedabus;
	
wire [31:0] qa, qb;


/*regN 
	ffA (abus, a, clk),
	ffB (bbus, b, clk),
	ffD (d, dbus, clk);
*/


mux2X1 muxb4alu(
	
.in1(signext),
	
.in2(pipedbbus),
	
.out(qb),
	
.sel(imm2)

);



regN ffA (abus, pipedabus, clk);

regN ffB (bbus, pipedbbus, clk);

regN ffD (d, dbus, clk);

assign qa=pipedabus;

alu32 alu(
	.out_d(d),
	.Cout(Cout),
	.V(),
	.a(qa),
	.b(qb),
	.Cin(Cin),
	.S(S),
	.shamt(shamt)
	
	);


endmodule
